The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device having a reduced number of high voltage transistors, thereby reducing the size of the semiconductor memory device.
A flash memory device is a kind of semiconductor memory device, and has a page buffer for programming mass storage data or reading data in a short period of time. Accordingly, a program operation or a read operation is performed in a page unit by the page buffer.
FIG. 1A is a view illustrating a conventional memory device. Here, FIG. 1A shows only a part of the flash memory device.
In FIG. 1A, the memory device includes a memory cell array 110 having a plurality of memory cells for storing data and a page buffer circuit 120.
The memory cell array 110 has a plurality of cell strings where memory cells are serially connected. Each of the cell strings is connected to a bit line.
The page buffer circuit 120 has a plurality of page buffers.
Each of the page buffers is connected to a pair of bit lines of the memory cell array 110. Each bit line pair includes an even bit line BLe and an odd bit line BLo, and the page buffer is connected to the even bit line or the odd bit line.
Each of the page buffers includes a bit line selecting circuit 121 for selecting the even bit line BLe or the odd bit line BLo, and a latch 222 for latching input/output data and assisting the program operation or the read operation.
The bit line selecting circuit 121 has first to fourth N-MOS transistors N1 to N4. Each of the transistors N1 to N4 is a high voltage transistor.
Gate voltage signals DISCHe and DISCHo are inputted to the first N-MOS transistor N1 and the second N-MOS transistor N2 to apply a voltage VIRPWR to a bit line that is not selected. Voltage signals BSLe and BSLo are applied to the third N-MOS transistor N3 and the fourth N-MOS transistor N4 to precharge or sense a selected bit line.
The flash memory device performs an erase operation of whole memory cells in a block unit to erase data stored in the memory cell array 110. To perform the erase operation, a high voltage of 20V is applied to a P well of the memory cell array 110.
FIG. 1B is a sectional view illustrating the memory device in FIG. 1A.
In FIG. 1B, an N well is formed on a substrate Psub, a P well is formed in the N well, and the memory cell array 110 is manufactured in the P well. This structure protects surrounding circuits from a high voltage applied to the P well when the erase operation is performed.
However, the high voltage applied to the P well is provided to the bit line in a forward direction when the erase operation is performed. In addition, the high voltage is applied to the bit line selecting circuit 121 in the page buffers connected to the bit line. Accordingly, the N-MOS transistors N1 to N4 of the bit line selecting circuit 121 should be manufactured with a high voltage N-MOS transistor.
The high voltage transistor is manufactured with a large length and width to tolerate the high voltage. Accordingly, when the number of high voltage transistors is increased, it is difficult to reduce the size of the memory device.